Timestamps use frame-level alignment: frame * 0.08s (8x subsampling × 160 hop / 16kHz)
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When VM=1, the protected-mode bit goes low and the Entry PLA selects real-mode entry points -- MOV ES, reg takes the one-line path. Meanwhile, CPL is hardwired to 3 whenever VM=1, so the V86 task always runs at the lowest privilege level, under full paging protection. The OS can use paging to virtualize the 8086's 1 MB address space, even simulating A20 address line wraparound by mapping pages to the same physical frames.
with: #anyMessage -> [:pattern | pattern where: [:node | node selector beginsWith: 'prim' ]];
await dropOld.writer.write(chunk1); // ok